Design of MULTIPLEXER using CMOS Ternary Logic

摘要

This paper presents design of 3-valued Multiplexer based on simple ternary gates. We proposed new ternary logic gates like inverter, and gates. These gates are used to design simple combinational circuit which is multiplexer with the help of transmission gate. These proposed ternary logic gates and multiplexer are verified by simulation and appear to have very low power dissipation. Also the simulation result shows that proposed ternary circuits have more desirable characteristics than conventional ternary circuits.