VLSI Implementation of Densely Packed Decimal Converter to andfrom Binary Coded Decimal using Reversible Logic Gates

摘要

The Binary Coded Decimal encoding has always dominated decimal arithmetic algorithms and their hardware implementation by virtue is ease of conversion between machine- and human-readable formats, as well as a more precise machine-format representation of decimal quantities. As compared to typical binary formats, BCD's principal drawbacks are a small increase in the complexity of the circuits needed to implement basic mathematical operations and less efficient usage of storage facilities. Due to importance such pro’s and con’s of BCD it is needed to convert them to decimal format and floating point decimal play important role present day arithmetic. This paper uses densely packed decimal encoding to store significant part of the decimal floating point number. And present day VLSI, low power is the major consideration for the Design. The reversible logic gates are the main source for designing the low power CMOS circuits, as it is not possible to realize quantum computing without them where the quantum computing the speed is the main parameter. This paper derives the reversible implementation of DPD converter to and from conventional BCD format. This conversion is implemented to the adder circuits where they follow BCD code for the arithmetic addition such that converting them to DPD (Densely packed Decimal) will result in the better storage capacity by decreasing the less density of storage devices for faster access to memory. The implementation of the adder circuit is carried in low power technique by using reversible logic gates in order to go for the complete low power design of the implementation.