High Performance Optimization Function for 32- Bits Microcontrollers in Key Scheduling of the Lightweight Cipher Algorithm CLEFIA

摘要

Objectives: This paper shows an optimized code for light-weight cipher algorithms, attempting to keep the balance between the use of resources and the communication speed. Methods/Analysis: A real performance analysis is applied to the cryptographic algorithm CLEFIA, under the standards by ISO/IEC 29192-2, by means of a code optimization for key scheduling through bit-oriented instructions. It is used the Freescale KL25Z development board for the measure of response times and the structural blocks’ execution times for the cipher algorithm. Findings: In this paper a bit-level optimization was sought over some operative structures of the algorithm, taking advantage of the 32-bit architecture in the development platform, generating this way a better response time for the application and an increase of the Throughput performance regarding the reference code by SONY. Novelty/Improvement: This application was developed so it can be used by many platforms into any electronic application, which requires an encryption process, where the use of a PC is not worthy because of the size and cost.