Loop Kernel Pipelining Mapping onto Coarse- Grained Reconfigurable Architecture for Data- Intensive Applications

摘要

Coarse-grained reconfigurable architectures (CGRA)provide flexible and efficient solution for data-intensiveapplications. Loop kernels of these applications always consumemuch execution time of the whole program. However, mappingloop kernels onto CGRA is still hard to meet performance/costconstraints. This paper proposes a novel approach forautomatically mapping loop kernels onto CGRA with loop selfpipeliningto optimize data-intensive applications. The problemformulation is shown first. Then we present the resource sharingand pipelining of lspCGRA, together with its template standard.Further, a loop kernel pipelining mapping is proposed. Theconclusions show that our approach gains less resourceoccupation by 16.3% and more throughputs by 169.1% thanprevious advanced SPKM.