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LLR-based Bit-loading Algorithm and its Applications to HomePlug AV over OPERA Power-line Channels with Impulsive Noise

机译:基于LLR的位加载算法及其在具有脉冲噪声的OPERA电力线信道上的HomePlug AV中的应用

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In this paper the higher data rate technology of HomePlug, called HomePlug AV, is tested over the power-line channel models proposed by the OPERA project coupled with the Middleton Class A impulsive noise model. In particular the DLC bit-loading algorithm is developed and the performance is analyzed in terms of throughput when different scenarios are considered. To better exploit the error correction capabilities of the turbo code, this bitloading algorithm attempts to maximize the throughput while guaranteeing a target BER over a set of sub-carriers using a new metric based on the LLRs. Simulations show that the effect of the impulsive noise can be reduced by inserting a clipping module before the OFDM demodulator, thus guaranteeing very promising throughputs even in the worst scenarios.
机译:本文在OPERA项目提出的电力线通道模型以及Middleton A类脉冲噪声模型的基础上,对称为HomePlug AV的HomePlug更高数据速率技术进行了测试。特别地,当考虑不同场景时,开发了DLC比特加载算法,并根据吞吐量分析了性能。为了更好地利用Turbo码的纠错能力,该位加载算法尝试使用基于LLR的新指标,在确保一组子载波上的目标BER的同时,最大化吞吐量。仿真表明,可以通过在OFDM解调器之前插入限幅模块来降低脉冲噪声的影响,从而即使在最坏的情况下也可以保证非常有希望的吞吐量。

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