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首页> 外文期刊>Defence science journal >Lead Chalcogenide on Silicon Infrared Focal Plane Arrays for Thermal Imaging(Review Paper)
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Lead Chalcogenide on Silicon Infrared Focal Plane Arrays for Thermal Imaging(Review Paper)

机译:用于热成像的硅红外焦平面阵列上的硫属元素化物铅(Review Paper)

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摘要

"Narrow gap IV-VI [lead chalcogenides like Pbl-xSnxSe and PbTe] layers grown epitaxially on silicon( III) substrates by molecular beam epitaxy exhibit high quality despite the large lattice and thermal expansion mismatch. A CaF2 buffer layer is employed for compatibility. Due to easy glide of misfit dislocations in the IV- VI layers, thei1rtal strains relax even at cryogenic. temperatures and after many temperature cyclings. The high permittivities of the IV- VI layers effectively shield the electric fields from charged defects. Higher quality devices are obtained from lower quality material, at variance to narrow gap 11- VI and 111- V compounds. Material characterisation and sensor array properties have been reviewed. Schottky barrier or p-n+ sensor arrays have been delineated using standard photolithography. At low temperatures, the sensitivities are limited by defects, mainly dislocations, and the device performance is predicted by the dislocation density. At higher temperatures, the ultimate theoretical sensitivity is obtained with Schottky barrier devices despite large mismatch and with only 3 μm thickness of the layers. First chara'cterisations of a 96 x 128 array on a silicon substrate containing the read-out circuits show that the concept is functional and gives high yield.
机译:“尽管晶格和热膨胀失配较大,但通过分子束外延在硅(III)衬底上外延生长的窄间隙IV-VI [硫族铅如Pbl-xSnxSe和PbTe铅层]表现出高品质,尽管CaF2缓冲层用于兼容性。由于IV-VI层中错位错位易于滑动,热应变甚至在低温,多次温度循环后也松弛,IV-VI层的高介电常数有效地屏蔽了电场,防止带电缺陷。从低质量的材料获得,并以窄间隙到11-VI和111-V化合物变化;已经审查了材料表征和传感器阵列特性;已使用标准光刻技术描绘了肖特基势垒或p-n +传感器阵列。灵敏度受缺陷(主要是位错)的限制,并且器件性能由位错密度预测。尽管失配很大,并且层的厚度仅为3μm,但使用肖特基势垒器件仍可获得最高的理论灵敏度。在包含读出电路的硅基板上对96 x 128阵列的最初特征表明,该概念是实用的,并且具有很高的良率。

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