A Novel Low-power Shared Division and Square-root Architecture Using the GST Algorithm

摘要

Although SRT division and square-root approaches and GST division approach havebeen known for long time, square-root architectures based on the GST approach havenot been proposed so far which do not require a final division/multiplication of the scalefactor. A GST square-root architecture is developed without requiring either amultiplication to update the scaled square-root quotient in each iteration or a division/multiplication by the scaling factor after completing the square-root iterations.Additionally, quantitative comparison of speed and power consumption of GST andSRT division/square-root units are presented. Shared divider and square-root units aredesigned based on the SRT and the GST approaches, in minimally and maximallyredundant radix-4 representations. Simulations demonstrate that the worst-case overalllatency of the minimally-redundant GST architecture is 35% smaller compared to theSRT. Alternatively, for a fixed latency, the minimally-redundant GST architecturebased division and square-root operations consume 32% and 28% less power,respectively, compared to the maximally-redundant SRT approach.