Implementation of PSK Digital Demodulator with Variable Rate Based onFPGA

摘要

Aiming at QPSK modulation digital system with variable rate, a novel implementation method based on fieldprogrammable gate array (FPGA) is proposed, which can support 4.88Kbps to 2Mbps and even higher continuous bit rate.The design adopts mixed multiplier, numerically controlled oscillator (NCO) and integral comb filter (CIC), and describesthe structure of carrier recovery circuit and signal recovery circuit, which can be ported to any FPGA device. The proposeddesign has its hardware test in the Xilinx Virtex-5 FPGA platform. The hardware test results show that the proposeddemodulator only takes up 15% available logical unit of Xilinx Virtex-5 FPGA device, revealing superior ability in efficiency.