Hardware Prototyping of Neural Network based Fetal Electrocardiogram ExtractionThe aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.
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机译：基于神经网络的胎儿心电图提取的硬件原型本文的目的是为FPGA（现场可编程门）使用VHDL（超高速集成电路硬件描述语言）从复合腹部ECG（AECG）提取胎儿ECG（FECG）的算法建模数组）实现。设计了一种人工神经网络，它提供了从复合AECG信号中分离FECG信号的有效方法。所提出的方法在FHR监测中R峰检测的准确度为93.7％。使用用于FPGA实现的Quartus II版本8.0 Web版，将设计的VHDL模型合成并安装到Altera的Stratix II EP2S15F484C3中。
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