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A PVT-Robust Super-Regenerative Receiver with Background Frequency Calibration and Concurrent Quenching Waveform

机译:具有背景频率校准和并发淬火波形的PVT鲁棒超再生接收机

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A process-voltage-temperature (PVT)-robust, low power, low noise, and high sensitivity, super-regenerative (SR) receiver is proposed in this paper. To enable high sensitivity and robust-PVT operation, a fast locking phase-locked-loop (PLL) with initial random phase error reduction is proposed to continuously adjust the center frequency deviations of the SR oscillator (SRO) without interrupting the input data stream. Additionally, a concurrent quenching waveform (CQW) technique is devised to improve the SRO sensitivity and its noise performance. The proposed SRO architecture is controlled by two separate biasing branches to extend the sensitivity accumulation (SA) phase and reduce its noise during the SR phase, compared to the conventional optimal quenching waveform (OQW). The proposed SR receiver is implemented at 2.46 GHz center frequency in 180 nm SMIC CMOS technology and achieves better sensitivity, power consumption, noise performance, and PVT immunity compared with existent SR receiver architectures.
机译:本文提出一种鲁棒的过程电压温度(PVT),低功耗,低噪声,高灵敏度,超再生(SR)接收器。为了实现高灵敏度和稳健的PVT操作,提出了一种具有初始随机相位误差减小功能的快速锁定锁相环(PLL),以在不中断输入数据流的情况下连续调整SR振​​荡器(SRO)的中心频率偏差。此外,还设计了并发淬灭波形(CQW)技术来提高SRO灵敏度及其噪声性能。与传统的最佳猝灭波形(OQW)相比,所建议的SRO体系结构由两个独立的偏置分支控制,以扩展灵敏度累积(SA)阶段并降低其在SR阶段的噪声。与现有的SR接收器架构相比,拟议的SR接收器在180 nm SMIC CMOS技术中以2.46 GHz中心频率实现,并实现了更好的灵敏度,功耗,噪声性能和PVT抗扰性。

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