Design of a Low-Power 1.65 GBPS Data Channel for HDMI Transmitter

摘要

This paper presents a design of low power data channel for application in High Definition MultimediaInterface (HDMI) Transmitter circuit. The input is 10 bit parallel data and output is serial data at 1.65Gbps. This circuit uses only a single frequency of serial clock input. All other timing signals are derivedwithin the circuit from the serial clock. This design has dedicated lines to disable and enable all itschannels within two pixel-clock periods only. A pair of disable and enable functions performedimmediately after power-on of the circuit serves as the reset function. The presented design is immune todata-dependent switching spikes in supply current and pushes them in the range of serial frequency and itsmultiples. Thus filtering requirements are relaxed. The output stage uses a bias voltage of 2.8 volts for areceiver pull-up voltage of 3.3 volts. The reported data channel is designed using UMC 180 nm CMOSTechnology. The design is modifiable for other inter-board serial interfaces like USB and LAN withdifferent number of bits at the parallel input.