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Reconfigurable Hardware Implementation of a Multivariate Polynomial Interpolation Algorithm

机译:多元多项式插值算法的可重构硬件实现

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Multivariate polynomial interpolation is a key computation in many areas of science and engineering and, in our case, is crucial for the solution of the reverse engineering of genetic networks modeled by finite fields. Faster implementations of such algorithms are needed to cope with the increasing quantity and complexity of genetic data. We present a new algorithm based on Lagrange interpolation for multivariate polynomials that not only identifies redundant variables in the data and generates polynomials containing only nonredundant variables, but also computes exclusively on a reduced data set. Implementation of this algorithm to FPGA led us to identify a systolic array-based architecture useful for performing three interpolation subtasks: Boolean cover, distinctness, and polynomial addition. We present a generalization of these tasks that simplifies their mapping to the systolic array, and control and storage considerations to guarantee correct results for input sequences longer than the array. The subtasks were modeled and implemented to FPGA using the proposed architecture, then used as building blocks to implement the rest of the algorithm. Speedups up to172×and67×were obtained for the subtasks and complete application, respectively, when compared to a software implementation, while achieving moderate resource utilization.
机译:多元多项式插值法是科学和工程学许多领域的关键计算,对我们而言,对于有限域建模的遗传网络逆向工程的解决方案至关重要。需要这种算法的更快实现来应对遗传数据的数量增加和复杂性增加。我们提出了一种基于Lagrange插值的多元多项式新算法,该算法不仅可以识别数据中的冗余变量并生成仅包含非冗余变量的多项式,而且还可以仅对精简数据集进行计算。该算法在FPGA上的实现使我们确定了基于脉动阵列的架构,该架构可用于执行三个插值子任务:布尔覆盖,唯一性和多项式加法。我们对这些任务进行了概括,简化了它们到脉动阵列的映射以及控制和存储注意事项,以保证输入序列长于阵列的正确结果。使用所提出的架构对子任务进行建模并实现到FPGA,然后将其用作构建块以实现算法的其余部分。与软件实现相比,子任务和完整应用程序的加速分别达到172×和67×,同时实现了中等的资源利用率。

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