Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform

摘要

Multi-FPGA hardware prototyping is becoming increasinglyimportant in the system on chip design cycle. However,after partitioning the design on the multi-FPGA platform, thenumber of inter-FPGA signals is greater than the numberof physical connections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowersthe system frequency. The way in which the design is partitionedaffects the number of inter-FPGA signals. In this work, wepropose a set of constraints to be taken into account duringthe partitioning task. Then, the resulting inter-FPGA signalsare routed with an iterative routing algorithm in order toobtain the best multiplexing ratio. Indeed, signals are grouped andthen routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routingproblem. Many scenarios are proposed to obtain the mostoptimized results in terms of prototyping system frequency. Usingthis technique, the system frequency is improved by an averageof 12.8% compared to constructive routing algorithm.