Implementation of High Speed, Low Power and Area Efficient Parallel Prefix Adder in an FPGA

摘要

In the portable world, the major issues in the designs are low power, high speed and less area requirement. Most of the portable computing devices contain the sophisticated and power hungry signal processing techniques, hence there is a need to reduce the power consumption of these devices. Binary adder is a fundamental unit in many arithmetic operations, and signal processing applications. Hence the impact of the adders will be large on the overall performance of the entire system. The aim of this paper is to present a low power, high speed and area efficient parallel prefix adder architecture. The proposed adder architecture is implemented for 16bit, 32bit width operands using Xilinx 14.5 version of VHDL with targeted device of Spartan 3E. The experimental results are compared with the basic adder variants such as Ripple Carry Adder, Carry Lookahead adder, Carry Bypass Adder, Carry Select Adder.