A mixed radix, floating point FFT processor is designed using radix-2 and radix-22 butterfly elements, adapting a pipelined architecture for a variable length of 128/512/2048. The single-path delay feedback (SDF) architecture is employed to exploit the symmetry in signal flow graph of FFT algorithm. Area minimization has been achieved for the reconfigurable FFT processor by using pipelining and higher radix butterfly structures. (radix-22). Then area power trade off is done with parallel mixed radix processing blocks, to achieve better throughput. A reconfigurable architecture has been achieved by bypassing certain processing blocks while keeping the other blocks functional through control mechanism. The proposed design is implemented in 45nm technology and the synthesis results show a silicon area of 4.7mm2 and a power consumption of 152mw at 50MHz and 208.5mw at 100MHz.
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