Design and Minimization of Reversible Circuits for a Data Acquisition and Storage System

摘要

Reducing power dissipation is the ultimate objective in the world of VLSI circuit design. Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. Thus reversible logic has become immensely popular research area and its applications have spread in various technologies. In this paper we have proposed the compact design of reversible circuits for a data acquisition and storage system. The design comprises with a compact reversible analog-to- digital converter and a reversible address register. In the way of designing this data acquisition and storage system we have proposed a reversible J-K flip-flop with asynchronous inputs, a reversible D flip-flop and a reversible three state buffer register. All the reversible designs individually have less number of gates, garbage outputs and quantum cost compared with the existing ones and have outperformed those described in the literature. Moreover we have proposed some lower bounds for designing these reversible components of the compact data acquisition and storage system.