Design and Analysis of Modified Fast Compressors for MAC Unit

摘要

Multiplication and addition are the basic arithmetic operations which are important in several microprocessors and digital signal processing (DSP) applications. As the demand for high speed multipliers is continuously increasing, the studies related to the field of multipliers and adders are endless and still significant. Compressors can be used with the aim of reducing the power dissipation of multipliers without compromising their speed performance in which only multiplexer and basic gates are used. In this work, different topologies of 42 and 52 compressors are compared in terms of power delay product and number of transistors. Compressor topologies are simulated in 90nm Technology using Cadence Virtuoso schematic editor at 700mV power supply. The improved design can be used in multipliers with minimum delay than conventional ones which can be used in MAC units applied for DSP applications.