A 16-Bit by 16-Bit MAC Design USING Fast 5:3 Compressor Cells

摘要

3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix, As a design example, a 16-bit by 16-bit MAC (Multiply and accumulate) design is investigated both in a purely logical gate implementation and in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3/100 speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 μm bulk CMOS technology, 11.7/100 speed improvement is observed with 8.1/100 less power consumption for the reduction Tree.