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Scalable design of microprogrammed digital FIR filter for sensor processing subsystem

机译:用于传感器处理子系统的微程序数字FIR滤波器的可扩展设计

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References(7) In this letter, a novel scalable and modular design of direct form sequential finite impulse response (FIR) filter using microprogrammed control unit is proposed that can be efficiently realized in field programmable gate array (FPGA) or application specific integrated circuit (ASIC). The proposed design is suitable for sensor processing subsystem used in wireless sensor network (WSN) nodes. This is demonstrated by evaluating a sample 4-tap FIR filter on various FPGA platforms and ASIC technologies. The evaluation result shows good area/power efficiency and flexibility by using microprogrammed architecture for such applications.
机译:参考文献(7)在本文中,提出了一种使用微程序控制单元的直接形式顺序有限冲激响应(FIR)滤波器的新颖可扩展和模块化设计,可以在现场可编程门阵列(FPGA)或专用集成电路( ASIC)。提出的设计适用于无线传感器网络(WSN)节点中使用的传感器处理子系统。通过评估各种FPGA平台和ASIC技术上的示例4抽头FIR滤波器,可以证明这一点。通过针对此类应用使用微程序架构,评估结果显示出良好的面积/功率效率和灵活性。

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