Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption

摘要

References(4) Cited-By(2) This paper describes a design methodology for determining the number of stages in a cascaded time amplifier to minimize the area consumption. The total area consumption is categorized into three parts, which allows mathematical analysis and optimization to be performed. A combination of the proposed mathematical analysis and 2D mapping can determine the number of stages to minimize the area consumption.