Flexible Medium Speed Systolic Architecture for FIR Filter Based onDistributed Arithmetic

摘要

This study proposes an innovative architecture for medium speed Finite Impulse Response (FIR) filterbased on Distributed Arithmetic (DA). This architecture composed of linear systolic arrays is derived by a twofactor decomposition of both the order of the filter and the length of the input sequence. Many variants ofmedium speed systolic structures are possible that depend on how the input word length is factored. Thedesign metrics, used to verify the effectiveness of the proposed architecture are the delay elements, speed interms of maximum frequency and area as the number of slices. This design is implemented on theXilinx Virtex-6 Field Programmable Gate Array (FPGA). A comparison of the performance metrics is made amongthe variants of medium speed architectures. The simulation results of the proposed design for different filtertaps when related to the existing low speed and high speed systolic architectures shows that it requiresintermediate area resources, latency and results in a medium speed. The implementation results also distinctlyexhibit that the proposed architecture requires less hardware resources and also yields remarkably highermaximum frequency for various filter orders when compared with an existing DA based medium speed FIR filter.