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Pulse Mode Neural Network Implementation for Handwritten Digit Recognition

机译:脉冲数字神经网络实现手写数字识别

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This study describes a new pulse mode artificial neural network (PNN) implementation based on floating point number format. For on-chip learning operations, the back-propagation algorithm is modified to have pulse mode operations for effective hardware implementation. By using floating point number system for synapse weight value representation, any function can be approximated by the network. The convergence rate of the learning and generalization capability is improved. The proposed network is applied for digit recognition application. The recognition approach is based on a series of features, which are at most independent of orientation and position. The most important featurea are based on Zernike moments. However, an exclusive use of Zernike moments in digit recognition increases tremendously the neural network size, since higher orders are needed to ensure best recognition rates. Moreover, given their geometrical invariance, Zernike moments give the same description to some different digits such as 6 and 9. Thus, we make use of other features based on structural descriptors witch are the terminating point number and the terminating location number which is orientation dependent. This features based presentation of the digits reduces the required Zernike order and the number of hidden layers and adds a great simplicity to the design, making possible the on-chip learning implementation for online operations. The proposed PNN is implemented on a Virtex II FPGA platform. Various experiments are carried on for design evaluation.
机译:这项研究描述了一种新的基于浮点数格式的脉冲模式人工神经网络(PNN)实现。对于片上学习操作,将反向传播算法修改为具有脉冲模式操作,以实现有效的硬件实现。通过将浮点数系统用于突触权重值表示,网络可以近似任何功能。学习和泛化能力的收敛速度得到提高。所提出的网络被应用于数字识别应用。识别方法基于一系列特征,这些特征最多与方向和位置无关。最重要的特征是基于Zernike矩的。但是,在数字识别中仅使用Zernike矩会极大地增加神经网络的大小,因为需要更高的阶数才能确保最佳识别率。此外,由于Zernike矩的几何不变性,它们对某些不同的数字(例如6和9)进行相同的描述。因此,我们基于结构描述符使用其他特征,它们是终点号和终点位置号,它们与方向有关。这种基于数字的特征表示减少了所需的Zernike顺序和隐藏层的数量,并大大简化了设计,从而使在线操作的片上学习实现成为可能。拟议的PNN在Virtex II FPGA平台上实现。进行各种实验以进行设计评估。

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