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首页> 外文期刊>American journal of engineering and applied sciences >Low Power Phase Locked Loop Frequency Synthesizer for 2.4 GHz Band Zigbee | Science Publications
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Low Power Phase Locked Loop Frequency Synthesizer for 2.4 GHz Band Zigbee | Science Publications

机译:用于2.4 GHz频段Zigbee的低功耗锁相环频率合成器|德州仪器TI.com.cn科学出版物

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> Problem statement: Wireless communication systems are required for many applications. There are different standards for these systems. IEEE 802.15.4 defines the communication system standard for zigbee. This study discussed designing one of the blocks of zigbee transceiver which is the Phase Locked Loop (PLL). A major target for any communication systems is saving battery power, especially for zigbee as it is meant to be a low cost communication system. Phase Locked Loop is responsible on carrier frequency selection in a communication system. It is the most power consumer block in the transceiver as well. The objective of this study was designing a low power fully integrated integer-N PLL frequency synthesizer targeting the 2.4 GHz band IEEE 802.15.4 Std zigbee. Approach: Minimizing total power consumption of PLL was achieved by introducing a novel design of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks. The proposed PFD uses only 12 transistors and it preserved the main characteristics of the conventional PFD with a simple architecture. The Charge Pump (CP) was single-ended source switch to save power and minimize mismatches. The Voltage Controlled Oscillator (VCO) spans from 4.737-4.977 GHz band using LC resonator. The VCO worked at double the frequency band to avoid local oscillator leakage and feed through. The integer N divider used a 15/16 dual modulus. Results: The proposed PLL was designed using Silterra 0.18 um CMOS process. It consumed 3.2 mW with 1.8 voltage supply. Phase noise is-113.4 dBc Hz-1 at 1 MHz. The proposed PFD works up to 2.5 GHz with free dead zone. The Charge Pump (CP) works with 20 uA. lock-in time is 25 us and total die area is 1×2 mm. All results were taken from extracted layout simulations. Conclusion: The results of this study indicated that a PLL can work with less power consumption and save the transceiver battery. The proposed PFD was suitable for high speed applications.
机译: > 问题陈述:许多应用程序都需要无线通信系统。这些系统有不同的标准。 IEEE 802.15.4定义了zigbee的通信系统标准。这项研究讨论了设计zigbee收发器模块之一的就是锁相环(PLL)。任何通信系统的主要目标都是节省电池电量,特别是对于zigbee而言,因为这意味着它是一种低成本的通信系统。锁相环负责通信系统中的载波频率选择。它也是收发器中功耗最高的模块。这项研究的目的是设计一种针对2.4 GHz频段IEEE 802.15.4 Std zigbee的低功率全集成整数N PLL频率合成器。方法:通过引入一个相位频率检测器(PFD)的新颖设计,并修改了其余PLL模块。提出的PFD仅使用12个晶体管,并且以简单的架构保留了传统PFD的主要特性。电荷泵(CP)是单端源开关,可节省功耗并最大程度地减少失配。使用LC谐振器的压控振荡器(VCO)跨度为4.737-4.977 GHz。 VCO工作在两倍频带,以避免本地振荡器泄漏和馈通。整数N分频器使用15/16双模。 结果:建议的PLL是使用Silterra 0.18 um CMOS工艺设计的。它在1.8电压电源下的功耗为3.2 mW。 1 MHz时的相位噪声为113.4 dBc Hz -1 。拟议的PFD在高达2.5 GHz的频率下具有自由死区。电荷泵(CP)的工作电流为20 uA。锁定时间为25 us,模具总面积为1 x 2毫米。所有结果均来自提取的布局模拟。 结论:这项研究的结果表明,PLL可以以更低的功耗工作并节省收发器电池。提出的PFD适用于高速应用。

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