Gate Leakage Reduction by Clocked Power Supply of Adiabatic Logic Circuits

摘要

Losses due to gate-leakage-currents become more dominant in new technologiesas gate leakage currents increase exponentially with decreasing gate oxidethickness. The most promising Adiabatic Logic (AL) families use a clockedpower supply with four states. Hence, the full V_DD voltage drops over anAL gate only for a quarter of the clock cycle, causing a full gate leakageonly for a quarter of the clock period. The rising and falling ramps of theclocked power supply lead to an additional energy consumption by gateleakage. This energy is smaller than the fraction caused by the constantV_DD drop, because the gate leakage exponentially depends on the voltageacross the oxide. To obtain smaller energy consumption, Improved AdiabaticLogic (IAL) has been introduced. IAL swaps all n- and p-channel transistors.The logic blocks are built of p-channel devices which show gate tunnelingcurrents significantly smaller than in n-channel devices. Using IAL insteadof conventional AL allows an additional reduction of the energy consumptioncaused by gate leakage. Simulations based on a 90nm CMOS process show alowering in gate leakage energy consumption for AL by a factor of 1.5compared to static CMOS. For IAL the factor is up to 4. The achievablereduction varies depending on the considered AL family and the complexity ofthe gate.