Implementation of Resource Sharing Strategy for Power Optimization in Embedded Processors

摘要

The processors are better suited to the diverse applications in daily life ranging from small toys to complex automated systems. For better mobility and reliability; the longer battery life is an essential need. Improvement in power efficiency of the processor is achieved by implementing resource sharing logic at the hardware level. This paper discusses the modified architecture of a 32 - bit RISC processor having four - pipeline stages. Here power improvement is achieved by implementing the proposed technique called resource sharing at the hardware level and results are verified satisfactorily. The proposed work is simulated, synthesized, tested and verified by using tools such as VHDL simulator, Xilinx Sparten – 3E FPGA, ModelSim SE-6.5 and Xilinx ISE – 13.1 tool and XPower Analyzer for power estimation and analysis purpose.