Multicore processors have become ubiquitous, both in general-purpose and special-purposeapplications. With the number of transistors in a chip continuing to increase, the number ofcores in a processor is also expected to increase. Cache replacement policy is an importantdesign parameter of a cache hierarchy. As most of the processor designs have becomemulticore, there is a need to study cache replacement policies for multi-core systems. Previousstudies have focused on the shared levels of the multicore cache hierarchy. In this study, wefocus on the top level of the hierarchy, which bears the brunt of the memory requests emanatingfrom each processor core. We measure the miss rates of various cache replacement policies, asthe number of cores is steadily increased from 1 to 16. The study was done by modifying thepublicly available SESC simulator, which models in detail a multicore processor with a multilevelcache hierarchy. Our experimental results show that for the private L1 caches, the LRU(Least Recently Used) replacement policy outperforms all of the other replacement policies.This is in contrast to what was observed in previous studies for the shared L2 cache. The resultspresented in this paper are useful for hardware designers to optimize their cache designs or theprogram codes.
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