A 10-bit 2.5 GS/s low power hybrid subranging flash-SAR ADC for high data rate communication

摘要

The growing need for power aware and energy efficient analog-to-digital converters (ADCs) has led to the development of optimized ADC designs. Though several ADCs are designed using isolated platforms, the usage of hybrid combination has noticeably made an impact in achieving this scenario. The proposed work herein is based on a subranging flash and successive-approximation-register ADC design. The isolated architectures have been redesigned and it is seen to be efficient with a power reduction by 40%. The utilization of comparator with a proposed charge sharing circuitry produces a lower input referred offset voltage during the comparison stages by eliminating the need of a extra circuitry. However, this increases the kick-back noise accounting for the sure trade-off. To reduce these effects a sample and hold switch is used at the comparator input voltage during the decision mode to minimize the kick-back noise thereby keeping the non-linearity errors at minimal. Energy efficiency of 64% have been seen compared to the referred design due to the proposed charge sharing circuitry during the evaluation phase. The converter achieves 61-dB SFDR and 46.5-dB SNDR at 2.5?GS/s for input signal frequency of 100?MHz with a power dissipation of 10.5?mW at 1 V supply.