FPGA-based optimal robust minimal-order controller structure of a DC-DC converter with Pareto front solution

摘要

This paper presents multi-objective optimization-based robust controller design of a DC-DC boost converter, controlled with FPGA (Field Programmable Gate Array). The main aim of the proposed design technique is to obtain a fixed and low-order robust controller which is reliable and easy to implement on a low-cost real-time digital system. The improved proposed control design method with direct closed-loop pole position assessment using metric L_2, is based on robust optimal regional closed-loop pole assignment technique. The optimal solution has been obtained using multi-objective Pareto front search genetic algorithm. This paper also presents simulated and practical experimental results with implemented optimized robust controller on FPGA, controlling the DC-DC boost converter. For the sake of comparison with the proposed controller design method, an additional auto-tuned PID controller has been designed along with robust controllers based on mixed sensitivity loop-shaping method.