FPGA technology mapping with encoded libraries and staged priority cuts

摘要

Synthesis flow involves translating a given design into an unbound logic network, followed by a technology mapping phase that targets different technologies and implementation styles. In the case of field-programmable gate arrays (FPGAs), this involves grouping various elements of the logic network into look-up tables (LUTs) and other structures like programmable logic blocks (PLBs). There are established algorithms for FPGA technology mapping targeting K -input LUTs that make use of feasible cuts at the nodes of the logic network to heuristically select good candidate cuts. Recent advances have demonstrated the efficiency and effectiveness of maintaining about four to eight priority cuts at the nodes instead of enumerating all the cuts.