Customized pipeline and instruction set architecture for embedded processing engines

摘要

This research aims to improve performance in embedded application domains. The authors have not proposed an entirely new set of instructions, but rather have customized instructions by building a dataflow graph (DFG) and profiling the application that is to be executed. In addition, they obtain various statistics from the applications, such as iteration frequency, basic blocks required, and dynamic execution blocks. Thus, by obtaining software latency from the code, they try to identify the hardware latency by the number of cycles. The number of basic inputs/outputs is identified from read/write operations from each block. If the number of inputs/outputs exceeds the available read/write ports of the register file that is available, then the pipelining method is used to improve the performance. With this method of performing multi-cycle read/write operations in order to stay within the register file limit, some performance loss happens. However, the method also helps to increase the bandwidth of the register file.