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In-line interrupt handling and lock-up free translation lookaside buffers (TLBs)

机译:在线中断处理和无锁转换后备缓冲器(TLB)

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摘要

The effects of the general-purpose precise interrupt mechanisms in use for the past few decades have received very little attention. When modern out-of-order processors handle interrupts precisely, they typically begin by flushing the pipeline to make the CPU available to execute handler instructions. In doing so, the CPU ends up flushing many instructions that have been brought in to the reorder buffer. In particular, these instructions may have reached a very deep stage in the pipeline - representing significant work that is wasted. In addition, an overhead of several cycles and wastage of energy (per exception detected) can be expected in refetching and reexecuting the instructions flushed. This paper concentrates on improving the performance of precisely handling software managed translation look-aside buffer (TLB) interrupts, one of the most frequently occurring interrupts. The paper presents a novel method of in-lining the interrupt handler within the reorder buffer. Since the first level interrupt-handlers of TLBs are usually small, they could potentially fit in the reorder buffer along with the user-level code already there. In doing so, the instructions that would otherwise be flushed from the pipe need not be refetched and reexecuted. Additionally, it allows for instructions independent of the exceptional instruction to continue to execute in parallel with the handler code. By in-lining the TLB interrupt handler, this provides lock-up free TLBs. This paper proposes the prepend and append schemes of in-lining the interrupt handler into the available reorder buffer space. The two schemes are implemented on a performance model of the Alpha 21264 processor built by Alpha designers at the Palo Alto Design Center (PADC), California. We compare the overhead and performance impact of handling TLB interrupts by the traditional scheme, the append in-lined scheme, and the prepend in-lined scheme. For small, medium, and large memory footprints, the overhead is quantified by comparing the number and pipeline state of instructions flushed, the energy savings, and the performance improvements. We find that lock-up free TLBs reduce the overhead of refetching and reexecuting the instructions flushed by 30-95 percent, reduce the execution time by 5-25 percent, and al-so reduce the energy wasted by 30-90 percent.
机译:在过去的几十年中使用的通用精确中断机制的影响很少受到关注。当现代乱序处理器精确地处理中断时,它们通常从刷新管道开始以使CPU可用于执行处理程序指令。这样,CPU最终将刷新许多已引入到重排序缓冲区中的指令。尤其是,这些说明可能已经进入了非常深入的阶段-表示浪费了大量工作。此外,在重新刷新并重新执行已刷新的指令时,可能会出现数个周期的开销和能量浪费(检测到异常)。本文着重于提高精确处理软件管理的转换后备缓冲器(TLB)中断的性能,该中断是最频繁发生的中断之一。本文提出了一种在重排序缓冲区中内联中断处理程序的新颖方法。由于TLB的第一级中断处理程序通常很小,因此它们可能与现有的用户级代码一起放入重新排序缓冲区中。这样做时,原本应从管道中冲洗掉的指令无需重新获取并重新执行。另外,它允许独立于异常指令的指令继续与处理程序代码并行执行。通过内联TLB中断处理程序,可以提供无锁定的TLB。本文提出了将中断处理程序内联到可用的重新排序缓冲区空间中的前置和追加方案。这两种方案是在加利福尼亚帕洛阿尔托设计中心(PADC)的Alpha设计人员构建的Alpha 21264处理器的性能模型上实现的。我们比较了传统方案,追加内联方案和前置内联方案处理TLB中断的开销和性能影响。对于较小,中等和较大的内存占用空间,开销是通过比较已刷新指令的数量和流水线状态,节能和性能改进来量化的。我们发现,无锁定的TLB减少了重新刷新和重新执行刷新指令的开销,减少了30-95%,执行时间减少了5-25%,并且还减少了30-90%的能量浪费。

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