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SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems

机译:SyRA:早期系统可靠性分析,用于微处理器系统内存阵列中的跨层软错误恢复

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摘要

Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessorbased system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. This paper proposes SyRA, a system-level cross-layer early reliability analysis framework for radiation induced soft errors in memory arrays of microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics. SyRA implements several mechanisms and features to deal with the complexity of realistic models and implements a complete tool-chain that scales efficiently with the complexity of the system. The simulation time is significantly lower than micro-architecture level or RTL fault-injection experiments with an accuracy high enough to take effective design decisions. To demonstrate the capability of SyRA, we analyzed the reliability of a set of microprocessor-based systems characterized by different microprocessor architectures (i. e., Intel x86, ARM Cortex-A15, ARM Cortex-A9) running both the Linux operating system or bare metal in the presence of single bit upsets caused by radiation induced soft errors. Each system under analysis executes different software workloads both from benchmark suites and from real applications.
机译:当可靠性是基于微处理器的系统设计时,跨层可靠性正成为首选解决方案。但是,决定如何在系统的不同层之间分配错误管理是一项非常复杂的任务,需要支持专用的跨层可靠性分析框架。本文提出了SyRA,这是一种系统级跨层早期可靠性分析框架,用于基于微处理器的系统的内存阵列中的辐射诱发的软错误。该框架利用多级混合贝叶斯模型来描述目标系统,并利用贝叶斯推理来估计不同的可靠性指标。 SyRA实现了多种机制和功能来应对现实模型的复杂性,并实现了一个完整的工具链,可以随着系统的复杂性而有效地扩展。仿真时间显着低于微体系结构级别或RTL故障注入实验,其准确度足以做出有效的设计决策。为了演示SyRA的功能,我们分析了一套基于微处理器的系统的可靠性,这些系统具有运行Linux操作系统或裸机的不同微处理器体系结构(即Intel x86,ARM Cortex-A15,ARM Cortex-A9)的特征。由辐射引起的软错误导致的单个比特不安。被分析的每个系统都从基准套件和实际应用程序执行不同的软件工作负载。

著录项

  • 来源
    《IEEE Transactions on Computers》 |2019年第5期|765-783|共19页
  • 作者单位

    Politecn Torino, Dept Control & Comp Engn, I-10138 Turin, Italy;

    Politecn Torino, Dept Control & Comp Engn, I-10138 Turin, Italy;

    Univ Athens, Dept Informat & Telecommun, Zografos 16122, Greece;

    Univ Athens, Dept Informat & Telecommun, Zografos 16122, Greece;

    Montpellier Lab Informat Robot & Microelect LIRMM, F-34095 Montpellier, France;

    Univ Politecn Cataluna, Comp Architecture Dept, Barcelona, Spain;

    Univ Politecn Cataluna, Comp Architecture Dept, Barcelona, Spain;

    Montpellier Lab Informat Robot & Microelect LIRMM, F-34095 Montpellier, France;

    Univ Lyon, Lyon Inst Nanotechnol, CNRS, UMR 5270, Lyon, France;

    Univ Politecn Cataluna, Comp Architecture Dept, Barcelona, Spain;

    Univ Politecn Cataluna, Comp Architecture Dept, Barcelona, Spain;

    Univ Athens, Dept Informat & Telecommun, Zografos 16122, Greece;

    Intel, Milan, Italy;

    Politecn Torino, Dept Control & Comp Engn, I-10138 Turin, Italy;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Reliability; cross-layer; microprocessors; soft errors; failures-in-time;

    机译:可靠性;跨层;微处理器;软错误;失败 - 时间;

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