Effective traversal algorithms and hardware architecture for pyramidal inverse displacement mapping

摘要

We present an effective traversal algorithm and a hardware architecture to accelerate inverse displacement mapping. This includes a set of techniques that are used to reduce the number of iterative steps that are performed during inverse displacement mapping. For this purpose, we present two algorithms to reduce the number of descending steps and two algorithms to improve the ascending process. All these techniques are combined; we observe up to 66% reduction in the number of iterative steps as compared to other pyramidal displacement-mapping algorithms. We also propose a novel displacement-mapping hardware architecture based on the novel techniques. The experimental results obtained from the FPGA and ASIC evaluation demonstrate that our novel architecture offers many benefits in terms of chip area, power consumption, and off-chip memory accesses for mobile CPUs.