机译:高吞吐量和面积效率的FPGA实现AES用于高流量应用
Univ Saskatchewan Dept Elect & Comp Engn Saskatoon SK Canada;
Univ Saskatchewan Dept Elect & Comp Engn Saskatoon SK Canada;
field programmable gate arrays; cryptography; logic design; telecommunication traffic; area-efficient FPGA implementation; AES-128; high-traffic applications; high throughput field-programmable gate array; advanced encryption standard-128; symmetric key encryption algorithm; FPGA efficiency cryptosystem; pipelining techniques; data throughput; add-round-key; shift-rows; Xilinx Virtex-5; VHDL; new-affine-transformation; frequency 622; 4 MHz;
机译:数据加密标准(DES)的高吞吐量和高效FPGA实现
机译:数据加密标准(DES)的高吞吐率和高效FPGA实现
机译:FPGA上AES算法的超高吞吐量和全流水线实现
机译:一种在FPGA上实现AES的高效区域改组方案
机译:128位AES算法的低功率FPGA实现
机译:遥感应用中基于FPGA的量化神经网络混合类型实现
机译:在FPGA上用于空间应用的面积有效的二维卷积实现