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首页> 外文期刊>IEEE Transactions on Circuits and Systems for Video Technology >A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding
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A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding

机译:MPEG-4形状编码的基于多符号上下文的算术编码架构

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MPEG-4 shape coding comprises context-based arithmetic encoding (CAE) as its centerpiece. Since the CAE algorithm has a complicated coding procedure and strong data dependency, it is hard to exploit its pipeline and parallel facilities. Furthermore, to encode multiple symbols within one clock cycle, it needs to overcome the issues of extracting multiple contexts of these symbols, deriving multiple probabilities from these contexts, and performing multiple multiplicative range update operations. This paper presents an efficient pipelined multisymbol CAE architecture for real-time MPEG-4 shape encoding. The proposed design is based on the inherent characteristics of binary alpha blocks as well as the numerical properties of the probabilities indexed by the contexts, and it is capable of encoding either a singe symbol or multiple symbols within each clock cycle. To overcome the aforementioned issues under the consideration of the hardware cost and the critical path delay, only symbols with a particular set of contexts are chosen to be processed simultaneously within the same clock cycle. Theoretical analysis shows that the majority of symbols have contexts belonging to this particular set, and therefore CAE processing can be significantly accelerated. An example VLSI implementation of proposed architecture that encodes two symbols within each clock cycle without sacrificing the clock rate can achieve a speedup of 1.47 in comparison with traditional CAE architectures. This particular two-symbol design can support MPEG-4 Main Profile at levels 3 and 4 under extreme and typical conditions, respectively. When synthesized from Verilog RTL design by using TSMC 0.35-/spl mu/m 1P4M CMOS technology, the design can run at 90 MHz.
机译:MPEG-4形状编码以基于上下文的算术编码(CAE)为核心。由于CAE算法具有复杂的编码过程和强大的数据依赖性,因此难以利用其流水线和并行设施。此外,为了在一个时钟周期内对多个符号进行编码,需要克服以下问题:提取这些符号的多个上下文,从这些上下文中导出多个概率,以及执行多个乘法范围更新操作。本文提出了一种用于实时MPEG-4形状编码的高效流水线多符号CAE架构。提出的设计基于二进制alpha块的固有特性以及上下文索引的概率的数值属性,并且能够在每个时钟周期内对单个符号或多个符号进行编码。为了在考虑硬件成本和关键路径延迟的情况下克服上述问题,仅选择具有特定上下文集合的符号以在同一时钟周期内同时进行处理。理论分析表明,大多数符号具有属于该特定集合的上下文,因此可以显着加速CAE处理。与传统的CAE架构相比,在不牺牲时钟速率的情况下在每个时钟周期内对两个符号进行编码的拟议架构的VLSI实现示例可以实现1.47的加速。这种特殊的两个符号的设计可以分别在极端和典型条件下支持3级和4级的MPEG-4 Main Profile。当使用TSMC 0.35- / spl mu / m 1P4M CMOS技术从Verilog RTL设计中合成时,该设计可以在90 MHz下运行。

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