Although much research has been done on efficient high-speednfilter architectures, much of this work has focused on filters withnfixed coefficients, such as Canonical Signed Digit coefficient filternarchitectures, multiplierless designs, or memory-based designs. In thisnpaper, we focus on digit-serial, high-speed architectures withnprogrammable coefficients. To achieve high performance goals, wenconsider both of algorithm level and architecture implementation levelnof FIR filters. In algorithm level, we reformulate the FIR formulationnin bit-level and take the associative property of the addition in bothnthe digit-serial multiplications and filter formulations. Innarchitecture level, we considered issues to implement the reformulatednresults efficiently. The issues include addition implementation, datanflow arrangements, and treatment of sign-extensions. Based on the abovenconsiderations, we can obtain a filter architecture withnaccumulation-free tap structure and properties of short latency,nflexible pipelinability and high speed. Comparing the cost andnperformance with previous designs, we find that the proposednarchitecture reduces the hardware cost of a programmable FIR filter tononly half that of previous designs without sacrificing performance
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