An 8-bit CMOS 3.3-V 65-MHz digital-to-analog converter with asymmetric two-stage current cell matrix architecture

摘要

This paper describes a 3.3-V-65-MHz 8-bit CMOS digital-to-analognconverter (DAC) with two-stage current cell matrix architecture whichnconsists of a 4-MSB and a 4-LSB current matrix stage. The symmetricntwo-stage current cell matrix architecture allows the designed DAC tonreduce not only the complexity of decoding logic, but also the number ofnhigh swing cascode current mirrors. The designed DAC with an active chipnarea of 0.8 mm2 is fabricated by a 0.8-Μm CMOS n-wellnstandard digital process. The experimental data shows that the rise/fallntime, the settling time, and integral nonlinearity/differentialnnonlinearity (INL/DNL) are 6 ns, 16 ns, and less than 0.8 LSB,nrespectively. The designed DAC is fully operational for the power supplyndown to 2.0 V, such that the DAC is suitable for a low voltage and a lownpower system application. The power dissipation of the DAC with a singlenpower supply of 3.3 V is measured to be 34.5 mW