Architecture of 23GOPS video signal processor with programmablesystolic array

摘要

This paper describes an architecture of 23GOPS real-time videonsignal processor. In order to achieve high computational power and highndata bandwidth for real-time video signal processing, we adopt a uniquenarchitecture based on a programmable systolic array with 90 videonprocessing elements (VPEs). The VPE array realizes high processingnability and high flexibility by a simple structure of the VPE and antime-division multiple-operation scheme. It allows the processor to benapplied to various real-time video signal processing like HD-TV (MUSE)ndecoding. The processor, called the digital filtering array, has beennfabricated in 0.35-Μm CMOS three-metal-layer technology and achievesn23GOPS at 129.6 MHz operating frequency. Four million transistors arenintegrated in 13.61 mm×13.07 mm die size