System-level test synthesis for mixed-signal designs

摘要

Hierarchical test approaches are a must for large designs due tonthe computational complexity and tight time-to-market requirements. Innhierarchical test synthesis, test design is conducted at a subsystemnlevel where the design complexity is manageable. For analog systems,ntests are generally designed at the basic block level. This papernoutlines a tool for translating basic block-level tests intonsystem-level tests for large analog systems. Computational effectivenessnis achieved by the use of high level models and by a pre-analysis of thensystem to identify feasible translation paths. A method to compute thenfault and yield coverages of the resultant system-level tests is alsonprovided in order to evaluate the translation. Experimental results shownthat test translation reduces design for testability overheadnsignificantly while satisfying coverage requirements