A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops

摘要

This paper presents an operational amplifier for a 1-V supply voltage. It comprises three gain stages with ac-boosting and buffered Miller feedback compensation circuits. The implementation uses a standard 0.35- $mu$m CMOS process (${rm V}_{TN}=0.6$ V and ${rm V}_{TP}=-0.72$ V). To accommodate maximum voltage headroom between power rails, a pseudo-differential structure is adopted in this amplifier. The large common-mode gain associated with the structure is suppressed by two common-mode stabilization loops. The amplifier driving 100-pF loads achieves a 4.3-MHz gain–bandwidth product. The settling time of a 1-${rm V}_{pp}$ input step signal is 1.1$~mu$s. The amplifier consumes 249 $mu$W and occupies 0.06-mm$^2$ silicon area.