Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time Modulators

摘要

The maximum sampling rate of a continuous-time $DeltaSigma$ modulator is limited by quantizer delay. Most conventional delay compensation techniques address less than a clock cycle of delay. A technique previously proposed for compensating quantizer delays in excess of a clock cycle in bandpass modulators involves a parallel feedback path that bypasses the quantizer. We analyze this technique for low-pass modulators and show that sampling rates hitherto not possible can be achieved. Design tradeoffs are investigated, and simulation results showing the effectiveness of the technique are given.