San Jose, Calif. - Cadence Design Systems, Inc., announced that Renesas Technology Corp. adopted the statistical static timing analysis technology from the Cadence~® Encounter~® digital IC design platform to be part of its next-generation design flow. This advanced statistical timing analysis and optimization technology allows Renesas to accurately account for the effects of process variability in its leading-edge 45 nm digital designs. Benefits include reduced silicon-failure risk, improved design robustness and convergence, enhanced quality of silicon, significantly faster turnaround time, and a streamlined sign-off flow.
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