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Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method

机译:可变性分解法分析N型场效应晶体管中较大的漏极电流可变性的起因

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摘要

The origin of larger on-state drain current (I_(on) variability in n-type field-effect transistors (NFETs) than that in p-type field-effect transistors (PFETs), is investigated by evaluating FETs fabricated using 65 nm technology. It is found that the larger I_(on) variability in NFETs is caused by not only the larger threshold voltage component but also the larger current-onset voltage component of the I_(on)variability in NFETs. Moreover, it is experimentally confirmed that I_(on) variability of NFETs can be reduced by the halo carbon co-implantation through the reduction of threshold voltage and current-onset voltage components of theI_(on)variability in NFETs.
机译:通过评估使用65 nm技术制造的FET,研究了n型场效应晶体管(NFET)比p型场效应晶体管(PFET)更大的导通状态漏极电流(I_(on)变化) 。发现NFET的I_(on)变异性较大,不仅是由于NFET的I_(on)变异性较大的阈值电压分量引起的,而且是由较大的电流启动电压分量引起的,而且,实验证实了通过减少NFET中I_(on)变异性的阈值电压和电流启动电压分量,可以通过卤碳共注入来降低NFET的I_(on)变异性。

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  • 来源
    《Annales de l'I.H.P》 |2010年第11期|p.114201.1-114201.3|共3页
  • 作者单位

    Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan;

    Institute of Industrial Science, The University of Tokyo, Meguro, Tokyo 153-8505, Japan;

    Institute of Industrial Science, The University of Tokyo, Meguro, Tokyo 153-8505, Japan;

    Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan;

    Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan;

    Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan;

    Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan;

    Faculty of Information Sciences, Hiroshima City University, Hiroshima 731-3194, Japan;

    Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan,Institute of Industrial Science, The University of Tokyo, Meguro, Tokyo 153-8505, Japan;

    Robust Transistor Program, Nano Silicon Integration Project, Research Department 4, MIRAI-Selete, Tsukuba, Ibaraki 305-8569, Japan;

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