A highly linear CMOS transconductance amplifier in 180 nm process technology

摘要

The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180 nm CMOS process technology with 1.8 V power supply. Simulation results show third order harmonic distortion (HD ₃) of −70 dB for 600 mV_pp input signal. For 1% transconductance variation the linear range is about 1.2 V_pp. The input referred noise of the transconductor is 70 nV/Ö{text Hz}70,hbox{nV}/sqrt{text {Hz}} at 10 MHz. The quiescent power consumption is only 450 μW.