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Analytical modeling of trilayer graphene nanoribbon Schottky-barrier FET for high-speed switching applications

机译:用于高速开关应用的三层石墨烯纳米带肖特基势垒FET的分析模型

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摘要

Recent development of trilayer graphene nanoribbon Schottky-barrier field-effect transistors (FETs) will be governed by transistor electrostatics and quantum effects that impose scaling limits like those of Si metal-oxide-semiconductor field-effect transistors. The current–voltage characteristic of a Schottky-barrier FET has been studied as a function of physical parameters such as effective mass, graphene nanoribbon length, gate insulator thickness, and electrical parameters such as Schottky barrier height and applied bias voltage. In this paper, the scaling behaviors of a Schottky-barrier FET using trilayer graphene nanoribbon are studied and analytically modeled. A novel analytical method is also presented for describing a switch in a Schottky-contact double-gate trilayer graphene nanoribbon FET. In the proposed model, different stacking arrangements of trilayer graphene nanoribbon are assumed as metal and semiconductor contacts to form a Schottky transistor. Based on this assumption, an analytical model and numerical solution of the junction current–voltage are presented in which the applied bias voltage and channel length dependence characteristics are highlighted. The model is then compared with other types of transistors. The developed model can assist in comprehending experiments involving graphene nanoribbon Schottky-barrier FETs. It is demonstrated that the proposed structure exhibits negligible short-channel effects, an improved on-current, realistic threshold voltage, and opposite subthreshold slope and meets the International Technology Roadmap for Semiconductors near-term guidelines. Finally, the results showed that there is a fast transient between on-off states. In other words, the suggested model can be used as a high-speed switch where the value of subthreshold slope is small and thus leads to less power consumption.
机译:三层石墨烯纳米带肖特基势垒场效应晶体管(FET)的最新发展将受到晶体管静电和量子效应(如硅金属氧化物半导体场效应晶体管所施加的缩放限制)的支配。已经研究了肖特基势垒FET的电流-电压特性与物理参数(例如有效质量,石墨烯纳米带长度,栅极绝缘体厚度)以及电参数(例如肖特基势垒高度和施加的偏置电压)的关系。本文研究并分析了使用三层石墨烯纳米带的肖特基势垒FET的缩放行为。还提出了一种新颖的分析方法来描述肖特基接触双栅三层石墨烯纳米带FET中的开关。在提出的模型中,假定三层石墨烯纳米带的不同堆叠结构为金属和半导体触点以形成肖特基晶体管。基于此假设,提出了结电流-电压的分析模型和数值解,其中突出了施加的偏置电压和沟道长度相关特性。然后将该模型与其他类型的晶体管进行比较。开发的模型可以帮助理解涉及石墨烯纳米带肖特基势垒FET的实验。结果表明,所提出的结构表现出微不足道的短沟道效应,改善的导通电流,现实的阈值电压和相反的亚阈值斜率,并且符合《国际半导体技术路线图》近期指南。最后,结果表明,通断状态之间存在快速瞬变。换句话说,建议的模型可以用作亚阈值斜率值较小的高速开关,从而降低功耗。

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