Chrestenson generalized Walsh transform factorizations for parallel processing imbedded implementations on field programmable gate arrays are presented. This general base transform, sometimes referred to as the Discrete Chrestenson transform, has received special attention in recent years. In fact, the Discrete Fourier transform and Walsh–Hadamard transform are but special cases of the Chrestenson generalized Walsh transform. Rotations of a base-p hypercube, where p is an arbitrary integer, are shown to produce dynamic contention-free memory allocation, in processor architecture. The approach is illustrated by factorizations involving the processing of matrices of the transform which are function of four variables. Parallel operations are implemented matrix multiplications. Each matrix, of dimension N × N, where N = pn, n integer, has a structure that depends on a variable parameter k that denotes the iteration number in the factorization process. The level of parallelism, in the form of M = pm processors can be chosen arbitrarily by varying m between zero to its maximum value of n − 1. The result is an equation describing the generalised parallelism factorization as a function of the four variables n, p, k and m. Applications of the approach are shown in relation to configuring field programmable gate arrays for digital signal processing applications.
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机译:提出了用于并行处理的Chrestenson广义Walsh变换分解,并将其嵌入在现场可编程门阵列上。近年来,这种一般的基础变换(有时也称为离散Chrestenson变换)受到了特别的关注。实际上,离散傅里叶变换和Walsh–Hadamard变换只是Chrestenson广义Walsh变换的特例。在处理器体系结构中,显示了p为任意整数的base-p超立方体的旋转可产生动态无竞争的内存分配。通过分解来说明该方法,分解涉及作为四个变量的函数的变换矩阵的处理。并行运算是通过矩阵乘法实现的。每个维度为N×N的矩阵,其中N = p n sup>,n个整数,其结构取决于变量参数k,该变量参数表示分解过程中的迭代次数。可以通过在0到n的最大值n-1之间改变m来任意选择M = p m sup>个处理器形式的并行度。结果是一个方程式描述了广义并行度因式分解为n,p, k em>和 m em>四个变量的函数。相对于为数字信号处理应用配置现场可编程门阵列,示出了该方法的应用。
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