A RS decoder for the DVB-C system based on the Matlab simulation of the channel outer coder of DVB-C system is designed.The implementation structure of RS decoder is introduced. Based on the modified Euclidean algorithm, the design is implemented with three pipelined to increase throughput, its feasibility and reliability are verified in the FPGA.%在对DVB-C系统信道外码的Matlab仿真的基础上,介绍了RS译码器各部分的实现结构,设计了一种用于DVB-C系统的RS译码器.基于改进的Euclidean算法,并用三级流水线结构实现以提高吞吐率,在FPGA中验证了设计的可行性与可靠性.
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