基于可重构计算技术的ASIP设计与实现

摘要

为了加速计算密集或数据密集类算法,设计了Kahn线程定义的虚拟指令,以及嵌入式粗粒度可重构阵列流水线处理器的体系结构.通过指令流水线设计,实现虚拟指令的并行执行,将指令级并行扩展为线程级并行.系统运行时,采用订阅/发布机制作为可重构阵列的通信机制,利用可重构系统可重复配置的特点,提高了系统的计算效率.通过仿真实验验证了基于可重构计算技术的流水线处理器结构的有效性.%In order to accelerate algorithm of computation-intensive and data-intensive, virtual instructions designed by Kahn thread and pipeline processor for embedded coarse-grained reconfigurable array are introduced. Instruction-level parallelism is extended to contain thread-level parallelism by design of instruction pipeline. Communication of reconfigurable array adopts subscribe/published mechanism. Finally, the simulation result validates the architecture of pipeline processor.