RSA算法中大素数硬件生成方法研究与设计

摘要

在RSA加密算法的硬件设计中,大素数的生成极为关键.为了提高RSA算法中大素数的生成效率,在传统筛法的基础上,提出了一种能自动生成确定性大素数的硬件实现算法-循环迭代法.该算法的硬件实现采用状态机架构,使用VerilogHDL语言描述,并通过Modelsim仿真.实验结果表明,使用该方法生成素数序列,具有快速准确、高效、易于硬件实现的特点,为RSA算法的使用提供了极大的便利.%As known that it' s very important to generate the big prime number during hardware design of RSA Encryption algorithms.In order to improve the efficiency of the RSA Encryption algorithm, a deterministic algorithm for hardware implementation of big prime number automatic generation is put forward, which is based on conventional screening methods.The state machine framework is adopted for hardware implementation of the algorithm with Verilog-HDL description language.The functional verification is done with Modelsim Simulation and the results show that it can generate a prime number sequence automatically, quickly and accurately.It provides big convenience for RSA algorithm application with this prime library.