基于修正离散功率级模型的数字DC-DC变换器设计

摘要

在高精度数字DC-DC变换器设计中,必须建立变换器功率级的精确模型.通过分析现有功率级离散模型与连续模型的拟合度,建立了拟合程度更高的修正离散功率级模型.为简化数字控制器设计,针对修正离散功率级模型,提出了一种含单一设计参数的数字补偿器设计方法,并分析了该补偿器对系统稳态和瞬态性能的影响.基于Altera Cyclone Ⅲ FPGA开发板,实现了数字Buck变换器,测试结果表明:1.8V输出电压下,电压纹波率小于1％；0.4 A负载电流跳变时,过渡时间为0.22 ms,实验结果证明了修正离散功率级模型的精确性及数字补偿器的有效性.%For high precision design of digital DC-DC converters, it is necessary to establish the accurate discrete model of power stage. A modified discrete model of power stage with high degree of fitting with continuous model in magnitude and phase is built after analyzing the present discrete power stage model. Based on the modified power stage model, a digital compensator with one design parameter is proposed to simplify the design process, and also the steady-state and dynamic performances of converters using this compensator are analyzed. The digital Buck DC-DC converters is implemented on FPGA (Altera Cyclone III), and the experimental results indicate that the output ripple rate is less than 1% for 1.8 V output voltage, the transitional time is 0.22 ms for 0.4 A load step change, and prove the accuracy of modified discrete power stage model and the validity of the proposed digital compensator.This work is supported by National Natural Science Foundation of China (No. 60972157).